1. Field of the Invention
This invention relates to data transfer between data processing systems and external peripheral devices, digital processing systems in general and computer systems.
2. Description of the Prior Art
Digital processors communicate with the external world through many means, such as interrupts, direct memory access (DMA) and programmed input/output (I/O) ports. For digital processors contained on a single chip or semiconductor substrate, the interface to the external world becomes more difficult because of the limited number of pins available on the chip package for this interface. Many schemes have been used to circumvent the problem of limited pins. One technique is to use the same I/O lines for both data and address. An extension of the technique is to use only 8 lines for 16 bits of data and 16 bits of address information. The 16 bit information is divided into two parts of 8 bit bytes. The most significant byte, the 8 bits contained in the upper part of 16 bit words, are normally transmitted first followed by the least significant byte, the 8 bits in the least significant portion of the 16 bit word. For a 16 bit memory access then, the sequence is to send first the most significant 8 bits of the address followed by the least eight significant bits of the address. Then on the same bus the data would be sent by/sending the first most significant 8 bits of the data then the least significant 8 bits. While this technique solves the problem of memory access with a limited number of pins in the interface, it does so in a manner that requires more time than is required for a single 16 bit transmission over 16 parallel data lines. Thus the first technique requires four cycles whereas the second technique requires only two. The first technique is therefore referred to as "quadruply time-multiplexing".